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always@(posededge clk) is the equvalent of a clocked process with if rising_edge(clk) in VHDL.
It's not exactly correct to say it "would raise 'TestSignal' one clock cycle after entering 'state=st5'". This is only true if state is set with the same clock edge. Generally, state can be set at any time between the previous and the present clock edge.
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Thanks FvM,
I understand that always@(posedge clk) is equivalent to clocked process with rising_edge(clk) in VHDL, that's why I think a registered output of FSM can be described directly by using
always@(posedge clk) (namely 'TestSignal' is supposed to rise in the following clock cycle if the state transits to st5 in the current clock cycle, not necessarily at clock edge), however in my experiment the output came out within the same clock cycle as the one where the state transits to st5. This is what confuses me.
I'v no idea what goes wrong, now in order to have a registered output, I need to raise a flag (combinatorial signal) when the state transit to st5, then use
always@(posedge clk) block to trigger the output TestSignal when the flag rises. Why can't I use always@(posedge clk) block to monitor the state directly?
Thanks
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