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Altera_Forum
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12 years ago

Sequential output of FSM in Verilog

Hi, I did a little experiment in Verilog as I set up a simple FSM and generate sequential output using the following code: always@(posedge clk) begin case(state) st5:begin ...
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Altera_Forum
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12 years ago

always@(posededge clk) is the equvalent of a clocked process with if rising_edge(clk) in VHDL.

It's not exactly correct to say it "would raise 'TestSignal' one clock cycle after entering 'state=st5'". This is only true if state is set with the same clock edge. Generally, state can be set at any time between the previous and the present clock edge.