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Altera_Forum
Honored Contributor
15 years agoYour YCbCr signal probably has a data rate of 27MHz (pixel rate x2). You need to create a signal that toggles at 13.5MHz to pick out every Y value from the data stream, because thats how fast it change.
All you need is a signal that looks something like this in VHDL:
process(clk, reset)
begin
if reset = '1' then
y_valid <= '0';
elsif rising_edge(clk)
y_valid <= not y_valid;
end if;
end process;
So in DSP builder you just need a register with the input being in inverted version of its output.