--- Quote Start ---
Of course there are clocks : read is read_clk,write is write_clk.They are different clock.
--- Quote End ---
And that will be a problem (i.e. more than one clock) when you get to trying to make this into a real device. Think about it a minute and ask yourself how is logic (in this case 'usedw') going to meet a setup or hold time requirement if it is clocked by different clocks
unless those two clocks happen to maintain a specific phase relationship to each other (for example, maybe one is exactly half the clock speed and edges are aligned).
This may or may not explain what you are seeing with simulation as well but if you're trying to make a real device you'll have to confront this issue sooner (i.e. now) or later. That's why I suggested a
single clock and FvM suggested 'a clock' (i.e. not more than one).
Kevin Jennings
Honored Contributor
