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Hi every one.
I wrote a verilog fifo including the following line:
always @(posedge read or posedge write or negedge rst)
begin
if(!rst)usedw<=8'h0;
else if(read==1'b1)begin
usedw <= usedw - 8'h1;
end
else if(write==1'b1)
begin
usedw <= usedw +8'h1;
end
end
When siimulating with Modelsim some strange thing happend that all the element usedw[] of usedw ware like self-oscillaton.
Is there any one who can tell me what's the reason?
An Altera's supportor said to me that it can be solved by adding contraints to the project.But I got the same results when I addeed sdc files.
Looking for help from you.
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What you've posted is not a synchronous fifo. You should have a single clock...
always @(posedge clock)
Then you use the read, write and reset in the logic.
You should also consider the condition when read and write are both true. In that situation, the correct operation is that usedw wouldn't change...in yours usedw will decrement by 1.
Kevin Jennings
Honored Contributor
