DrewBaden
New Contributor
6 years agoSee "details".
# Reading D:/Altera/13.1/modelsim_ase/tcl/vsim/pref.tcl # do top_run_msim_rtl_verilog.do # if {[file exists rtl_work]} { # vdel -lib rtl_work -all # } # vlib rtl_work # vmap work rtl_work # ...