Securely start a State-Machine with pulses or edges

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This is something I normally don't use

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For any asynchronous input it is a must.

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But I think my filtered edge-detection is somehow similar to that.

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No it is not unless you use the output of second synchroniser and discard others in the synchroniser chain.

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The problem is between two cores inside the FPGA. Both cores are on the same clock and are working on the same edge (falling_edge).

So I think the signal must already be synchronized.

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still it does not explain how the start_in comes in.