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Altera_Forum
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11 years ago

Securely start a State-Machine with pulses or edges

Hi there, this problem occures in my work from time to time: I want to start a State-Machine (Transition from Idle-State S000 to State S010) either with a single one-clock-pulse or on the edg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This is something I normally don't use. But I think my filtered edge-detection is somehow similar to that.

The problem is between two cores inside the FPGA. Both cores are on the same clock and are working on the same edge (falling_edge).

So I think the signal must already be synchronized.