Forum Discussion
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- Hi kaz, yes it is. I already mentioned it above. --- Quote End --- I meant do you use two stage synchroniser on start_in e.g. on clock edge: start_1d <= start_in; start_2d <=start_1d; then use start_2d as input to state machine(not start_1d, nor start_in) and make sure start_in is of enough duration to be sampled