Securely start a State-Machine with pulses or edges

I can't agree with you because the core normally starts ery well, except for about 1 out of 100 to 1000 tries. This could be caused by a clock-glitch, but they are on the same clock, so there can be no glitch.

If my state-machine is kind of messed up, wouldn't this cause much more errors?

Besides, I've already checked if the state-machine is in an other state than the idle-state when the Start_IN comes. -It isn't.

My cores process a message from outside the FPGA. The outside "Logic" (Processor) sends one message and the waits for the result (answer-message) before sending the next message. If the processor is done receiving the answer, every core in the FPGA is already in idle-state. So I assume the state-machines are working well.

Except that it can occure, that one of the cores seems to "miss" its start-signal and so the message is lost.