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Altera_Forum's avatar
Altera_Forum
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10 years ago

Securely start a State-Machine with pulses or edges

Hi there, this problem occures in my work from time to time: I want to start a State-Machine (Transition from Idle-State S000 to State S010) either with a single one-clock-pulse or on the edg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

if its from another core inside the same FPGA on the same clock, then I suggest there is a problem with the statemachine logic - its not that it is "not seeing it", there is a bug in your code - either this block or the other one.