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Altera_Forum
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11 years ago

Securely start a State-Machine with pulses or edges

Hi there, this problem occures in my work from time to time: I want to start a State-Machine (Transition from Idle-State S000 to State S010) either with a single one-clock-pulse or on the edg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

assuming start_IN is fully synchronous to your 125MHz clock, then your problems are problems with your design, not the fact it is being "missed". Logic never misses anything.

If startIN is not fully synchronous, then you may be getting some meta-stable values on sig_start_in(0) or bouncing when you shift it into your shift register (so you dont get a clean "0011"). I suggest synchronising the signal first.