Second opinion on timequest constraints

Very clear now, thanks Rysc. Much obliged.

Any thoughts on the value of using multicycle (= 2) to transition between domains of related clocks of different frequencies? Example: signals passing between domains of Clk_75 and Clk_100 which are both derived from the same 150 MHz clock. I have seen this done but have some doubt about "best practise". My concern is particularly when vectors are passed without any handshaking. One needs to be sure that all bits of the vector arrive on the same clock edge. Is adding handshaking and treating them asynchronously (as unrelated clocks with double registers on the handshake lines) a better option?

Perhaps this should have been a different thread - sorry Ardni, if I am highjacking your topic, but one thing leads to another...