Second opinion on timequest constraints

Thank you SlowClock and Rysc for the replies.

Initially I was unsure about the legality of implementing the multicycle as I did and still I do not have it clear in my own head. Here is what is confusing me:

Rysc you said that "clocking on the falling edge(before the multicycle) hurts your setup requirement, but helps your hold". I am clocking the data from the FIFO to the DAC data bus on the rising edge, so would this multicycle not help my setup time (if the DAC registers on the falling edge) ? i.e. it gives me an extra half cycle and with a 150MHz clock give me a default setup time of 9.99ns up from 6.66ns?

I didn´t really understand what you meant by "I recommend registering your data on the way out"? Do you mean removing the multicycle and clocking on the following rising edge.

Without the multicycle it seems to be very difficult to meet setup time. I am still not 100% clear if using the multicycle as I have is illegal, if it is merely shifting the same size window by one cycle, then it should be ok?

I´m probably wrong but I´d be grateful if someone could clarify these points.

Many thanks for the help so far.