Honored Contributor
Honored ContributorSorry, Ardni, but I have some doubts. If you specify multicycle=2 you tell TimeQuest that from the time the source register is clocked anything is allowed to happen (i.e. data invalid) on the input of the destination register until Tsu before the second clock edge of the destination clock. This only works if you have an enable on the destination register which you know (from the logic of your design - perhaps a state machine) will not be enabled during the first clock edge of the destination register.
In your case the destination register is external (in the DAC) with no enable. You care about what data is on the register input at every clock cycle, therefore multicycle is not appropriate. Coincidentally I am currently wrestling with a project I inherited where the designer misused multicycles in the same way. It is great for making the timing violation seem to go away - for a while :-). What to do? I recommend you clock the DAC on the same edge as the source register. By using the opposite edge you perhaps gave yourself less time. You may also want to add extra delay in your set_output_delay statements reflecting the trace delay on your board, i.e. the tracks between the two chips. I am hoping someone cleverer will check what I have just written, and comment.
