second if loop is not working in verilog and latches are generated .how to fix these?

001 and 010 are interpreted as decimal. 'Choice' is 3 bits, it cannot represent decimal 10. If you mean binary, they should be 3'b001, and 3'b010. All 0s are a result of initialization.

Other than 001 and 010, there is no default value assigned to reg_result. Thus, synthesis needs to preserve reg_result if 'choice' is not 001 or 010. Therefore results in latches.

If combinatorial logic is what you look for, you can make following changes

always @* // Use '*' to indicate comb logic, synthesis tool will complain if you code wrongly

begin

reg_result = 9'h000; // Or some other default values if 'choice' is not 001 or 010

// Put your old codes here

end

By the way, the 'data1' is 7 bits, not sure it is intentional or typo. A good practice is to keep the arguments passed into task has matching bus width.