SDRAM Model with protected code cannot be compiled

Hello,

I try to compile this Verilog model: https://www.winbond.com/hq/product/specialty-dram/sdram/?__locale=en&partNo=W9864G6JT

With Questa 2021.2 and Modelsim 10.5b I am not able to compile this model for my simulation.

I get the following errors:

# ** Error: W9864G6JT.vp(110): (vlog-2109) `protected block is corrupted.
# ** Error: W9864G6JT.vp(111): (vlog-2163) Macro `<protected> is undefined.
# ** Error: (vlog-13069) W9864G6JT.vp(111): syntax error in protected region.
#
# ** Error: W9864G6JT.vp(111): (vlog-2163) Macro `<protected> is undefined.
# ** Error: W9864G6JT.vp(111): (vlog-2163) Macro `<protected> is undefined.
# ** Error: W9864G6JT.vp(111): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?

I also recognized that the protected section is added with verilog 2005 and you can only select verilog 2001.

I hope somebody figured this out and can help.