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Altera_Forum's avatar
Altera_Forum
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12 years ago

SDC set_input_delay and set_output_delay constraints

Hello, I'm new to TimeQuest / SDC commands. In my design I've got an external Ethernet switch device that is sourcing a dedicated clock signal to drive data into an FPGA. The switch device al...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Ohh. I am crazy..

But I agree with Rbugalho.

Outputmax=14

Outputmin=4

If clk is going out from eth chip to fpga with 2ns board trace, and if data is going out from fpga to eth chip with 2 ns board trace..

Tnx to all!