Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorTo Ryan's point about scripting with set_input_delay or set_output_delay, that's why we recommended setting up a virtual clock. As long as you have a virtual clock constraint for whatever is driving the upstream or downstream device, you can create set_input or set_output_delay constraints and make them generic.
