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Altera_Forum
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8 years ago

[SDC] Input/Output delay for All ports -> script writing

Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Yes, it has timing arcs and basically the model. Note that it also sets the model used, e.g. Slow 100 corner, or something like that.

It is not recommended to embed constraints. There was a way to do it but it's really ugly and it has no scope(so it doesn't just apply to the file it's in, but is read like a generic constraint). Altera used to use this internally, but now tries to create an explicit .sdc for all IP and include it with a .qip file.