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Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorWhat actually does the command create_timing_netlist? Does it create a seperate Netlist with timing arcs?
In the read_sdc command, there is a switch '-hdl': read_sdc -hdl. as far as I understand it gives an option to read SDC commands from HDL. So, how is it possible to embed SDC commands into HDL? Could you provide an example please?
