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Altera_Forum's avatar
Altera_Forum
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8 years ago

[SDC] Input/Output delay for All ports -> script writing

Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Why this order? Intuitively I'd do it in this order:

read_sdc

create_timing_netlist

Why this order will not work?

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You have to create the timing netlist before you can apply the sdc commands to it ... doesn't work the other way around.