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Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Why this order? Intuitively I'd do it in this order: read_sdc create_timing_netlist Why this order will not work? --- Quote End --- You have to create the timing netlist before you can apply the sdc commands to it ... doesn't work the other way around.
