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Altera_Forum
Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorIf run from a script, then the following are necessary:
set projname [lindex $quartus(args) 0] set numpaths [lindex $quartus(args) 1] project_open $projname Most scripts I run I launch TimeQuest on the project and double-click on Update Timing Netlist, which does the following: create_timing_netlist read_sdc set_operating_conditions -model slow -grade c update_timing_netlist At that point I run a timing analysis script or whatever I need to do.
