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Honored Contributor
Honored Contributor[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_ForumHonored Contributor
Honored ContributorI tried to run the ferst example:
---------------------------------------------------------------------- set chan [open "TQ_all_clocks.rpt" "w"] foreach_in_collection element [all_clocks] { puts $chan [concat $element : [get_object_info -name $element]] } close $chan ---------------------------------------------------------------------- The 'all_clocks' command is not recognized (ran from the Tcl Console). I've got the following: ---------------------------------------------------------------------- Error:ERROR: Quartus Prime Tcl command "all_clocks" is only available for use in the following executables: Error: quartus_fit Error: quartus_sta Error: while executing Error:"all_clocks" Error: invoked from within Error:"foreach_in_collection element [all_clocks] { puts $chan [concat $element : [get_object_info -name $element]]}" ---------------------------------------------------------------------- So, what's the problem? How could be fixed? Thank you!
