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Altera_Forum
Honored Contributor
8 years ago[SDC] Input/Output delay for All ports -> script writing
Hi All, How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)? Let's say the design has the following clocks: clk0, clk1, clk2 ...
Altera_Forum
Honored Contributor
8 years agoset_input_delay [get_ports * ] ... =====>the * wildcard covers all the input ports
remove_input_delay [get_ports clk] ===> will remove the input delay on the specified port Same thing for output delay. http://quartushelp.altera.com/15.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_remove_input_delay.htm