ContributorHi All,
When SDC file used in the Quartus Compilation Flow?
As for my understanding, they are used:
- during the logic synthesis phase (timing/constraints-driven synthesis)
- during the logic cells placement/routing (?)
- during the Timing Sign-Off phase
Is that correct? Do the same SDC files are used during all the above phases?
Thank you!
Super ContributorYes, yes, yes, and yes. Unless there's something in the file to have it not use a constraint (like an over constraint that should not be used during timing analysis), the same files are used throughout.
ContributorHow is it possible to distinguish between the regular and over-constraints? Is there any argument, which should be used with the over-constraints, that tell the tool do not use it during the timing analysis?
Regular ContributorMy Quartus designs typically have three files:
o DESIGN.qpf ... the Quartus Project File, which just sets the project revision
o DESIGN.qsf ... the Quartus Settings File, which has most of the Quartus "set_xxx ..." commands
and
o DESIGN.sdc ... the Synopsys Design Constraints file, which has timing related commands like
create_clock, set_input_delay, set_false_path, etc
Each of the tools (quartus_map, quartus_fit, quartus_asm, quartus_sta, quartus_eda) have access to all
of the above files via the DESIGN.qpf/qsf/sdc file(s), so theoretically each tool can use any file contents
as it sees fit.
Regular ContributorHello,
Does the above reply answer your question?
Regards,
Nurina
Regular ContributorHello,
We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey
Regards,
Nurina
ContributorI've tried to add comments to this case in the link, which you provided, but the 'Post' bottom is in grey (in the Timeline section), so I cannot add any comments there ... how to solve ?
Regular ContributorHi,
Have you tried refreshing the page? Can you post a screenshot of that? I will report this problem to internal team.
Regards,
Nurina
ContributorNow it works... Posted my question there ....
Regular ContributorHi,
Why don't you want the overconstraints to be used during timing analysis? What do you what these to do, and/or which point of the compilation do you want it to be used?
Regards,
Nurina
Regular ContributorHello,
Is this what you're looking for? It applies during fitter rather than timing analysis.
Regards,
Nurina
Regular ContributorHi,
We do not receive any response from you on the previous answer provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey
Regards,
Nurina
