Forum Discussion
amildm
Contributor
ContributorSDC directives in HDL
Hi All,
Is it possible to add the SDC directives (e.g. set_false_path) directly in HDL?
Thank you!
FvM
Super Contributor
Super ContributorThere's different syntax for Verilog-1995 and Verilog-2001/SystemVerilog. The latter places the attribute before the module declaration. Please review the user manual.
