SDC directives in HDL

Hello,

a simple example. You have a synchronizer register in a VHDL entity and want a set_false_path statement added for each instance in the design automatically. As SDC uses hierarchical object names, the entity name must be unique.

ARCHITECTURE rtl OF ce_sync IS
   SIGNAL ce_toggle  : STD_LOGIC := '0';

attribute altera_attribute : string;
attribute altera_attribute of rtl : architecture is 
   "-name SDC_STATEMENT ""set_false_path -from [get_registers *ce_sync:*|ce_toggle]""";

Multiple SDC statements can be placed in the attribute statement by string concatenation.

Regards

Frank