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Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Then, do you consider clock_virtual as being asynchronous to clock_x? My question is about setting the clock groups with the set_clock_groups command. --- Quote End --- No. clock_virtual is the launch edge. clock_x is the latch edge. You would not cut these clock domains from each other.
