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Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- With regards to your original question here, the answer is neither. You should be adding a virtual clock constraint to define the external clock that is driving the upstream device that is providing signal_x to the FPGA. --- Quote End --- virtual clock is another option, not a must.
