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Altera_Forum
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15 years ago

Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

Over the past 30 years I've seen languages come and go. I started programming in assembler, and have since graduated to many 2nd and 3rd generation languages. I tend to shy away from 4th generation...
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Altera_Forum
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15 years ago

Hi BuGless. This is mainly about your comment about old timers thinking parallel(overlapped) design. The attached .qar is for what I dubbed CEngine which is a cpu that does if/else, for, do/while, function/subroutine call, and expression assignment. Also there is a .txt which is a cycle log showing some code and the cycle by cycle execution. (I hope both are attached).

One other significant point is that DCT and Xilinx just made news in EE Times with a Java cpu.A while ago I posted CEngine in this forum and got 1 response but maybe this time.

The design is not completely connected on the bdf, but there is a running "simulator".

Variables are in a 3 port ram so the first two operands are immediately available when the statement and operator appear. In parallel if there is a conditional jump that address is available at the end of the first execution cycle. If the jump is not taken the next statement i available so branch or not, it takes one cycle.