Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

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But like so much software, I've seen HDL code that's poorly structured, uncommented, and with hidden complexities and interlocking states that cannot be easily understood at a glance.

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I have some example of old schematics based FPGA designs that are uncommented, unmaintainable and extremely difficult to understand when you aren't the person who wrote them. What's your point? You can write bad code in any language, and have schematics that look more like a spaghetti plate than hardware. Similarly you can have very clean schematics or very elegant HDL code.