--- Quote Start ---
I think thats rather unfair. Technology today is much different. People have to deal with generating large multi-dimensional filters with complex memory controllers and other complex interfaces (as an example). Id hate to see anyone try to create large FPGA designs using 74 series chips. The best engineers I know still understand all the old school stuff, but are much happier today in the HDL world. They all know what kind of resource usage they will be looking at without even writing a word of HDL code.
--- Quote End ---
There is no fair/unfair about it--it's a worldview transition. To those of us who have run the evolution spanning TTL-PAL-GAL-PLD-CPLD-FPGA, we see the advantages of staying close to the hardware, whether the ultimate design connectivity be with discrete wires, fuses, or LUT patterns and routing channels.
I'm not going to fall for the "let's all return to the 7400 logic era" straw man. I was there, and, barring a few clever things done very efficiently with a few gates & FFs, those were not the good old days.
But, abandoning a fundamental understanding and feel for hardware, moving incrementally away from a GUI-based design (schemata) into reams of code, leaving everything to be sorted by some magic compiler, seems imprudent and risky. Funny how GUI is all the rage in so many technical arenas, yet engineers are being squeezed ever more into command-line, lines-of-code abstractions.
Hardware engineers generally favor assembler programming because it's closer to the hardware. Software wonks don't care as long as they get to play with highly-abstracted structures: just throw more memory and peripherals at them to keep 'em happy--let the compiler do the dirty work. Same with the FPGA specialist nowadays: just another wonk cranking out code.
And I'll contradict you on being "much happier" in HDL land--if I were so delirious with joy I wouldn't be writing this. Sure, HDLs solve problems in parameterization and state machine design that would be intractable and unmaintainable with primitives. But like so much software, I've seen HDL code that's poorly structured, uncommented, and with hidden complexities and interlocking states that cannot be easily understood at a glance.
Not everybody is doing million-gate, high-volume designs, yet for FPGA companies like Altera that's where the money is. They want to kick small operators into the gutter to save a few bucks, fine. But just because some pointy-haired VP thinks it's okay while cashing in his bonus does not IMO compensate for the loss of goodwill toward what is becoming just another FPGA vendor, rapidly losing its edge.
//atemp99
Honored Contributor
