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You forget that one of the biggest reasons for creating VHDL/Verilog was ostensibly to get a bunch of S/W people coding H/W designs. That, at least, was the "pie in the sky" vision being pitched by Cadence 10+ years ago.
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This is still an important, possibly overriding factor. I remember quite well the visionaries promoting the repurposing of C++ commodity programmers into hardware "designers". The takeover just happened to be with VHDL etc.
HDLs make designs less dependent on "gurus" who actually understand hardware, unlike many young pups just out of school, reared on VHDL or Verilog, who couldn't design a 7-segment decoder by hand to save their life, or understand how a JKFF state machine works (actually, I thought JKFFs sucked: once you have DFFs there's no going back IMO).
The gurus only design compilers now. Rooms full of cheap "paper clip" pseudo-HW engineers crank out the HDL, having only a hazy idea of how their stuff will be expressed in the actual hardware.
//A
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