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Actually, When I wrote my post I was from the POV of someone who implements FIRs, downsamplers etc. I HATE implementing individual bits with schematics. connecting individual registers and logic gates is a waste of time. This is what I think Simknutt is trying to talk about, rather than higher level connections.
But when it comes to higher up the hierarchy I can see the advantages. Im just limited to HDLs so I can actually simulate a connected design. I will often create a document of the basic layout schematic though so others can try and see the layout - be it either something I draw or the existing simulink model.
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I think it's the basic data flow that you generate and I won't argue HDL for that part although grabbing the mega functions and lpm's onto a bdf and sliding them around to form the picture is my preference. It is OK that they are coded in HDL. Then I can connect them with busses and only draw physical busses where I like.
The point of being limited to HDLs and the connected design and what I think is verbose text. Define a module, list the input ports, output ports, the edge of the clock used, I don't know what else, then an if condition(s) to describe the logic, then the name of the register. And that still does not connect the modules ports to the other modules ports. Hopefully simulink helps with this.
We used to pencil in Boolean expressions on complex control lines to have a concise description of the control then probe to see which condition was incorrect. Worked!
OOP languages have scope resolution operators for connecting objects, maybe as simple as a composite name with the module name '.' register name . So the syntax I have suggested: name of the register or bus to be assigned followed by ':' then the name of the register or buss used for input followed by '?' and the Boolean condition that controls/enables the assignment. Then back to the block diagram that has the clks and data inputs, add the control Boolean to the enable and the functional connection is done, but for simulation, the conditional assignment statement is used for input to a rather simple simulator that draws a functional waveform much as the designer might draw by hand to understand a particular event.
Then comes the messy part, that's the cloud of combinatorial control logic that leads to spaghetti tangles.
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