Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

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Actually, When I wrote my post I was from the POV of someone who implements FIRs, downsamplers etc. I HATE implementing individual bits with schematics. connecting individual registers and logic gates is a waste of time.

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The lowest level I normally go during entry is the individual LPMs Quartus II already provides. The trick obviously is to build up sane (usually meaning that there are few inputs and outputs) logic blocks which can be reused as larger blocks in the next hierarchy level. I.e. in that way, most of your design is designed at higher levels.