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I have a simulator prototype attached...
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I have to admit that I probably won't have time to properly look into this until after my current project is finished. I like toying with new ideas, but sometimes work comes first.
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That is because the hardware is parallel, and the objective of HDL is to use sequential if's to define parallel and gates. In a schematic you can follow a clock line and see everything it triggers. In hdl you have to find all the always blocks where the clock appears in the text and there has to be an always block for practically every register.
Why would anyone want to look at a block symbol shape, see 4 inputs, and immediately realiz that 4 signals are being and'd. It is more of a challenge to count the if statements.
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No argument here, I think we approach this in similar ways. Even though I have a vast experience in designing (large project) software and basically are proficient in reading through large amounts of source; I prefer the schematic approach in case of a circuit design.
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Remember also that synthesis is in there anxious to throw away the logic that you don't have totally connected so that it can see that it drives an output pin. And it may or may not generate the logic that you wanted. And placement and routing also waste compile time by running while the design is not logically complete. I have been called an idiot for complaining about synthesis throwing logic away that did not drive an output pin because all I was doing was wasting precious power. So I cannot put in incomplete logic to get a resource count for sizing purposes.
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This I solve using a wildcard virtual pin assigment which will make sure that any output which I don't assign to a real pin, is at least not optimised away.
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