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From My POV - drawing schematics becomes extremly unwieldy as designs become more complex (and I have seen large complex designs created with schematics). You could argue you just break it up into smaller chunks, but then you get into a massive heirachy, which can be just as bad.
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I realise that any method of describing things can be used in improper ways, but I would suspect that if done with equal care and consideration, a properly created schematic hierarchy will be more readable than an equally proper equivalent piece of HDL (yes, I know this doesn't hold for all cases, there undoubtedly are situations where HDL is superior in clarity).
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The great thing about VHDL/Verilog is that it allows you to write more behavioural like code to avoid the stupidly complex diagrams or large hierarchies. Synthesisors and parts are pretty good at laying this into logic on chips at a decent clock speed (if you're working at <100MHz, you can get away with quite long logic chains between registers).
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I wholeheartedly agree that certain pieces of logic are easier described using HDL, however that doesn't preclude that it is equally possible to describe functionality in a hierarchical schematic with the knowledge that the same compiler/optimiser as for HDL will reduce and integrate the schematic into something more efficient than the bare schematic would indicate. The difference between HDL and schematic entry in this case is though that when I use schematic entry I can largely predict what the total delay of the logic is going to be; when using HDL it is more of a surprise as to what comes out.
But, yes, at the end, the current portability of HDL is something which is hard to beat with schematic entry.
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