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@SimKnutt,
You forget that one of the biggest reasons for creating VHDL/Verilog was ostensibly to get a bunch of S/W people coding H/W designs. That, at least, was the "pie in the sky" vision being pitched by Cadence 10+ years ago. The tools, especially synthesis, have evolved at a much less than stellar rate (being kind here).
With parallel software coding becoming a required skill, perhaps things will get better. I sure hope so!
Cheers,
--slacker
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Everything I have seen goes back to variable assignment which is a small subset of what needs to be done. The decision(control logic is what uses the most time but does not benefit.
C2H is for optimizing computations. The high level synthesis (systemC?) stuff focuses on computation. Probably the classic boon-dogle was IBM's Stretch where pipelining and look-ahead was invented. It could not get out of its own way when someone fed it a program with conditional branches every few instructions. Of course many think that pipelining is great because of the high clock rate. Generally it uses a lot of power and extra registers that do not significantly increase overall performance.
The kind of thing I focus on is getting the two operands necessary for a typical operation.
The true dual port ram(3port) is my favorite. Only 2 are needed and they can be accessed very quickly in any combo. No routing, placement, wiring stuff, or timing.
This is the kind of parallelism that works and has nothing to do with what the program is trying to do. Works for compares(decisions) as well as assignments.
Honored Contributor
