Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

It sounds like a religious war, a lot has to do with tool support and the different vendors.

But before we throw our hands up and surrender, I have a scenario based on things I have first hand knowledge about. In the 1980's IBM was the largest manufacturer and user of semiconductors. The mainframe design methodology had a logic design phase and a physical design phase. The hand drawn logic was manually translated to text so the automated logic diagrams could be printed on a line printer that had some special graphic characters used to draw lines. What's the point? Hardware used logic gates to do logic, programmers understood if/else kind of things, everyone knew that a series of if blocks could represent an and block, so there was a common way to communicate logic.

The hardware was put into flow chart format that made sense to the programmers.

An algorithm was invented for a simulation program that did cycle simulation, and the logic was in a form that could be stored on a computer. That format became the basis for VHDL. And yes, that was a big deal. Remember there was a logic design phase? I was overlooked when all the attention was focused on the new thing. Today the design is compiled to rtl in order to be simulated in the process it is analyzed, synthesized, placed, routed, timing analyzed, and then simulated(there may be some shortcuts, but not obvious) Logic design is an iterative process(it evolves) so this process is repeated over and over. And synthesis helps by throwing away logic that does not drive IO. IO assignment should be a part of physical design. I am getting to the point that there are HDL standards, but there should be tool standards, then you could switch vendors.