Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

http://mysite.verizon.net/vzeosqt4/embeddedcengine has demo/example downloads that I think will run and show at least the concept. The number of cycles and 200 Mhz clock are the key points.

I see no appropriate forum to use for further discussion, and I am not a website designer so cannot take that route. Tried open source, but don't have skill to handle a repository. I would like to make one last point. Schematics have not gone away they are called rtl/netlists or whatever and the process of starting with HDL to compile and synthesize is really a slow process to draw a schematic. Programming in general is to solve a problem in sequential steps, which is not the way chips work. Therefore Verilog has the always block to pass the parallel function on to RTL, but it is a description language rather than an application language and that is why designers are using embedded processors to provide application function, it is not to implement complex hardware functions .. they are still combos of and, or and not. That has been the case until now and for the foreseeable future.