Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

You mentioned 30 years, I wrote my first logic simulator about 1970. And would like to offer something more than rhetoric. First I refer to "a new processor" thread I started in about February. I used embedded memory clocks, an adder, comparator, a few counters all entered on a .bdf. A string parser generated memory loads for the microprogrammed engine that ran the C code. There is no intermediate or typical machine language because the if/else/for/while things are directly implemented. kaz, a guru, and I had some exchanges and he cried a lot about the plight of the designer being at the mercy of what is available, but that he would never consider using someone else's design. No other replies.

I proposed a prototype Verilog simulator that parsed and evaluated code directly without the costly compile/synthesize/rtl process that takes so much time for function simulation. Vaughn, the head of Altera programming thought it was too much like System C.

I have a working logic simulator that uses a clock definition for each clock domain in the design so that the registers following the clock def are controlled by that clock. Statements similar to C conditional assignment contain the Boolean control and the data flow operators for each register.

This forum is probably nit the place, but I am willing to at least put up some demo/prototype code.

Any interest/suggestions (including FUGGIT ABOUT IT) are welcome.

PS There is a trend to use embedded processors when the complexity taxes the limits of HDL so I wonder if the thousands of lines of code and comments project could have used a processor? Of course that usually means programming in C and the pointer arithmetic and memory leak problems surface. Well Google has a new language, Go, that eliminated pointer arithmetic and has some other good features although it cannot handle memory mapped IO because it cannot access hardware. Sounds like a an opportunity to define a variation for use in embedded.