Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

I think there is more agreement than I expected. Also think it's time for me to go away, Thanks to all. Here are some things I will ponder.

1. What is the first step in a design documentation? Block diagram? HDL code?

2. One complex design has thousands of LOCs .. half of which are comments to explain the verbose HDL.

3. HDL should be used because the vendors support it better. Why? The tools are built by software types that only understand if/else.

4. If I want to use Boolean for a control condition if(a==1 && b==0 || a==0 && b==1)

then s = 1; ... if(a^b = 1) then s = 1; ... s = a^b ... ???

5. How many times should I specify that the always block is triggered with the clock edge

even if there is only a single clock and trigger type in the whole system?

Naw ... I cannot even list the questions, Goodbye everyone!