Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

I also forgot to mention the difficulty simulating schematic designs. Its fine just using the "convert to HDL" feature, but what about when I want to test a design in isolation using models for other design parts for extra speed of simulation?

and also what happens when a company drops support for some schemtic elements, or schematics altogether (like the LPM library in quartus schematics). You're stuck using an old version, or if a company goes bust - no software at all!