Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

Stephen,

I wouldn't let me scare off too much by Daixiwen's experience.

If you plan carefully (as anyone should do whatever design method used) you can develop a nice top-down viewable bottoms-up designed system.

The only restriction on ports in the BDE is that they must be either std_logic, std_logic_vector or std_logic_2D. And I haven't managed yet to pass an array of integers in the generic/parameter section. Connecting record ports like Tricky (and FvM) want is not possible, A workaround is to 'flatten' the record into a std_logic_vector and std_logic_2D in the case of an array of records. I can understand why one wants to use records, saving time typing in all those intermediate signal names. Where in a schematic all you have to do is to draw a wire or a bus.

If you really need to 'switch' between vendors you should look into Altium. Their schematic editor seamlessly transitions into FPGA-design, and they support Altera and Xilinx (possibly others too).