Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

I am somneone new to this game. I started VHDL 6 years ago during my degree course as part of my final year project. Now in industry, we use simulink, and there is pressure from above to use simulink for all new designs.

I have spent a year trying to use simulink's HDL coder, and finding it has many limitations over hand coded VHDL. It appears to be good if you dont mind it sprawling itself all over some big FPGA, but when you are limited to a specific FPGA from the start, where 90%+ is going to be used up from an efficient design, code-generationg isnt really suited to the job. Simulink is great as a verification environment, but hasnt proved itself to me as an efficient implemenation tool.

I have also battled through some more legacy designes done here with a mix of AHDL and Quartus scematic entry. These are probably examples of bad coding in any language, but having to follow signals around to see what they actually do, with little documentation, is not much fun. Then you have bits tacked on the design with comments like "equalises pipeline delay", without refering to what it is equalising with.

One strength in VHDL I have loved recently is it's ability to cope with complex types and ports to minimise the port connections.

I have the following record type:

type subband_t is record
  data : sfixed(12 downto -4);
  valid : std_logic;
  pos   : pos_track_t;
end record subband_t;
type subband_array_t is array(0 to 31) of subband_t;
signal subbands : subband_array_t;
.....then in the port mappings:
port map (
subbands => subbands,
...
);

Is about as clean as it gets, inside VHDL or schematic.

And to top it all off - at the end of the day, I dont need a $2k/5k/10k licence to edit my text files!