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HDL is a force fit and I am thankful not to have been brainwashed into believing in it.
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HDL's can NOT replace a designers insight into what circuits he/she intends to generate. HDL is "bull**** in bull**** out". You have to know what you are doing when writing VHDL or Verilog, you have to know what kind of circuit the synthesis tool will generate for you. If you do not know that by any approximation, then most often the circuits that you generate will be very complex and inefficient.
The Quartus manual helps to introduce this insight.
An other way to learn this insight is by regularly looking at the RTL Viewer to see what circuits are being generated.
Honored Contributor
