Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

I used a bdf and Megawizard for a design and got the benefits of the libraries without writing HDL at all. Then after compiling/synthesizing found that the netlist viewer showed the gory details in a giant "schematic". So the concerns about the volume of paper are greatly exagerated, just think of e-paper and netlist viewer. I never completed the design for other reasons, but I am convinced that schematic entry worked on I think Quartus 9.1. Since the lpm blocks seem to have disappeared in the last release, I am no longer a customer.