Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

Those (several A3 pages long schematic designs) sound like the equivalent of a program consisting of just one function of several thousand lines long.

The summary/consensus which I seem to hear here is that parameterisation support in schematics is bad to non-existent, and that there is no consistent schematic-fileformat with which to exchange designs between tools/vendors. Other than that, navigating and/or visualising a properly hierarchical/modular schematic design (possibly using HDL in some/all of the leaf-modules) would be better than using straight HDL only.

Overall, it helps me understand the (to some extent) sorry state of affairs around the available design tools currently.