Schematic entry (4th generation) vs. VHDL/Verilog (3rd generation)

@SimKnutt,

You forget that one of the biggest reasons for creating VHDL/Verilog was ostensibly to get a bunch of S/W people coding H/W designs. That, at least, was the "pie in the sky" vision being pitched by Cadence 10+ years ago. The tools, especially synthesis, have evolved at a much less than stellar rate (being kind here).

With parallel software coding becoming a required skill, perhaps things will get better. I sure hope so!

Cheers,

--slacker